1. Field of the Invention.
The invention relates to the field of priority interrupt systems in a data processing network.
2. Prior Art.
Many interrupt schemes have been implemented in the past to control the accessing of data in a computerized system. Fixed, as well as programmable, priority interrupt systems are available. As data acquisition rates increase with faster processors and the emergence of the 32-bit processors, faster priority interrupt schemes are needed. Earlier schemes allowed single word transfers only. That is, the system would look for an interrupt and allow a one word transfer per interrupt. This scheme is deemed to be slow in that appreciable finite time is required for handling each interrupt and also in that the system must respond to each interrupt as though it is coming from a separate device.
One means of increasing the speed of the acquisition rate involves block segment transfers. Block segments containing multiple words are transferred to a single device. Typically, a block transfer interrupt signal will lock out the system, such that only one device can access the memory during a complete block transfer. However, this scheme prevents interrupts from occurring during the block transfer.
The present invention allows for both single and multiple word (block segment) tranfers of data between a device and a memory. The present invention represents a departure from previous technologies and describes a scheme wherein a priority logic unit provides for two levels of priority depending on the type of transfer desired. A modified priority scheme also allows for uninterrupted block segment transfers as well as interrupted block segment transfers.